ASIC front-end Design Engineer

Exciting opportunity for an ASIC Design Engineer to define and architect high-performance blocks for advanced networking ASICs. Collaborate with cross-functional teams to deliver high-speed solutions. Ideal for candidates with strong Verilog RTL coding skills and experience in ASIC design for networking protocols.

Skills

• verilog rtl coding
• asic design
• networking asics
• synopsys design compiler
• verplex lec
• spyglass
• ethernet protocols
• memory subsystems
• multi-domain clock synchronization
• high-speed serial interfaces
• problem solving
• asic debugging
• fcoe
• testplan development
• timing analysis
• timing correction
• written communication
• verbal communication
• team collaboration
• leadership