Lead Physical Design Engineer
About Fractile
Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.
The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.
We are seeking a highly skilled Lead Physical Design Engineer to contribute to our next-generation chip designs. As a Lead Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off. In this role, you will take on leadership responsibilities across multiple dimensions, including full-chip ownership, leading a team of physical design engineers, and contributing to broader chip-level physical design leadership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.
Key Responsibilities:
- Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
- Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.
- Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
- Own power planning and analysis, addressing IR drop, electromigration, and related effects.
- Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
- Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
- Develop and improve flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
- Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
- Mentor junior engineers and contribute to building strong physical design practices across the team.
- Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Proven ability to take ownership of complex designs and drive them to completion.
• Experience mentoring engineers and leading physical design efforts.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.
