Sign up free to see how well your resume matches this role.
Mixel Vietnam is an innovator of high-performance analog mixed-signal semiconductor IPs, powering Mobile, Display, Camera, Automotive, VR, AR, and AI applications. As a member of Mixel Group and part of Silvaco Group (USA, NASDAQ: SVCO), we bring together the agility of a focused IP house with the scale, technology, and global reach of a leading EDA and semiconductor IP provider.
Our mission is to deliver outstanding, silicon-proven mixed-signal IPs that give our customers and partners a clear technology advantage. We invest in our people the same way we invest in our IPs — with discipline, care, and a long-term view.
At Mixel Vietnam you will find an environment built on technical excellence, employee well-being, minimal management layers, and the freedom to make meaningful contributions. We value open communication, empathy, mutual trust, and respect.
Circuit Design & Implementation
Design and own memory circuit blocks at transistor level — row/column decoders, wordline drivers, pre-charge, sense amplifiers, write drivers, self-timed replica/tracking paths, control logic, level shifters, and IO — to the performance, power, and area targets defined in the specification.
Support instance and compiler development: implement and update designs so they remain correct and margin-clean across the configuration range of the compiler.
Execute ECOs and design changes for device sizing, connectivity, and margin fixes, and drive them through to clean re-verification.
Own a complete memory instance or compiler sub-family end to end, including its architecture choices, margin strategy, and PPA trade-offs.
Simulation & Verification
Run pre- and post-layout SPICE simulation across all required PVT corners; verify function, timing, power, and leakage against specification.
Perform margin and statistical analysis — Monte-Carlo, bitcell read/write/hold margin, sense-amplifier offset, VMIN and retention analysis — and document the results for design review.
Close post-layout issues with the Layout team: parasitic impact, EMIR violations, coupling, and power-integrity findings.
Debug design mismatches and drive root-cause analysis together with the Modeling, Layout, and CAD teams.
Define the verification and corner strategy for the blocks under ownership, and review the simulation work of other engineers.
Automation & Methodology
Develop scripts and automation (Perl/Python/TCL/Shell/SKILL) to accelerate simulation, data collection, and regression tasks, and integrate them within the memory compiler / view-generation environment.
Follow and contribute to the design checklists, review gates, and sign-off criteria used by the Memory team.
Introduce and implement methodology improvements that enhance design quality and overall team efficiency.
Collaboration & Support
Work in close cooperation with Memory Layout, Modeling, DFT, Physical Design, and STA teams to deliver on time and according to required specifications, and escalate technical risks early.
Generate the required documentation, support characterisation and silicon correlation, and contribute to the validation and debugging of fabricated silicon.
Participate actively in design reviews — present your own work, and give and receive technical feedback constructively.
Provide mentorship and technical guidance to junior circuit engineers and interns.
Essential Requirements
BS/MS in Electronics Engineering, Telecommunications, Microelectronics, Computer Engineering, Physics, or a related field.
Minimum 4 years of hands-on custom/analog circuit design experience for IC or IP design
Proficient in schematic capture (Cadence Virtuoso or equivalent).
Proficient with spice simulators (hspice, spectre or equivalent) and multi-corner PVT simulation.
Working knowledge of statistical analysis for circuit design: Monte-Carlo, process variation, margin and yield concepts.
Experience with post-layout simulation, parasitic extraction, and basic EMIR analysis.
Experience with FinFET or advanced planar technologies.
Strong scripting/programming skills (Perl, Python, TCL, Shell) on Unix/Linux.
English Language Proficiency: Fluency, written and verbal.
Strong communication, analytical, and problem-solving skills.
Desirable Requirements
Direct experience on embedded memory (SRAM, DPRAM, ROM, Register File, or TCAM)
Master’s degree in Electronics / Microelectronics Engineering.
Hands-on experience with memory compilers and view-generation flows.
Understanding of memory bitcell behaviour and assist techniques (wordline boost, negative bitline, VDD collapse).
Familiarity with CCS/NLDM characterisation, Liberty (.lib) model generation, and SPICE correlation, or with DFT/MBIST for memories.
Understanding of memory architectures (SRAM/ROM/Register File), RTL modelling (Verilog, VHDL, Verilog-A), and STA concepts.
Knowledge of functional safety (ISO 26262) and quality (ISO 9001) processes.
