Senior Emulation / Pre-Silicon Validation Engineer (Cadence Palladium)
About this role
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฎ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ณ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฎ๐ฌ-๐ณ๐ฑ ๐๐ฃ๐)
Experience: 6+ yrs
Location: Bengaluru
Job Type: Full-time
We are seeking a highly skilledย Senior Emulation / Pre-Silicon Validation Engineerย to support pre-silicon validation for complex ASIC and SoC designs using advanced hardware emulation platforms. This role is ideal for professionals with deep expertise in Cadence Palladium environments, hardware/software co-validation, and SoC debugging who are passionate about accelerating silicon validation and improving product quality before tape-out.
As a Senior Emulation / Pre-Silicon Validation Engineer, you will collaborate closely with RTL, Verification, Firmware, Architecture, and Software teams to build scalable emulation environments, enable efficient hardware/software integration, and validate complex SoC functionality. You will play a key role in optimizing emulation workflows, debugging functional issues, developing transactors, and ensuring robust pre-silicon validation across multiple subsystems.
Requirements
Key Responsibilities
- Develop, maintain, and optimize hardware emulation environments using Cadence Palladium platforms.
- Support Palladium build, compilation, partitioning, clocking, and debug flows for large-scale ASIC and SoC designs.
- Design and develop SystemC/C++ transactors, reference models, and validation infrastructure.
- Enable and support ICE (In-Circuit Emulation) and Virtual Interface (VIF)-based validation environments.
- Perform hardware/software co-validation by integrating firmware and software with emulated hardware platforms.
- Debug functional, integration, and performance issues across hardware and software components.
- Collaborate with RTL, Verification, Firmware, and Architecture teams to accelerate validation and issue resolution.
- Develop automation scripts using Python, TCL, Perl, or Shell to improve validation efficiency and regression execution.
- Analyze validation results, identify root causes, and recommend improvements to emulation methodologies and workflows.
- Contribute to continuous enhancement of pre-silicon validation processes, emulation infrastructure, and overall verification productivity.
What Makes You a Great Fit
- 6+ years of experience in ASIC/SoC Emulation, Pre-Silicon Validation, or Hardware Validation.
- Strong hands-on expertise withย Cadence Palladiumย platforms, including XP, Z1, Z2, or Z3.
- Experience with Palladium compilation, partitioning, advanced clocking, ICE, and Virtual Interface (VIF) workflows.
- Proficiency inย SystemC,ย C/C++, and scripting languages such asย Python,ย TCL,ย Perl, orย Shell.
- Solid understanding of SoC architecture, hardware/software co-validation, and embedded system debugging.
- Experience validating high-speed interfaces such asย AXI, PCIe, DDR, USB, SPI, or similar industry-standard protocols.
- Strong debugging, analytical, and problem-solving skills with the ability to resolve complex integration issues.
- Familiarity with FPGA prototyping, UVM, Lauterbach, JTAG, CoreSight, ARM/x86 platforms, or networking ASICs is an added advantage.
- Excellent communication and cross-functional collaboration skills with experience working alongside design, firmware, and verification teams.
- A proactive mindset with a passion for improving validation methodologies, automation, and overall product quality.