The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
The US base salary range for this full-time position is $168,800 - $198,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google.
Position reports to the Google Portland, OR office & may allow for a hybrid schedule as per Google policy.
Responsibilities:
- Develop, analyze, optimize, or verify custom silicon chips for data centers and consumer devices, or create innovative networking technologies for Google’s custom chips.
- Complete object-oriented design verification.
- Develop cutting-edge networking hardware and software to ensure fast, reliable connectivity across our global infrastructure.
- Design and build servers, storage systems and other hardware components optimized for data centers, or work on custom silicon for Google’s products and other consumer devices.
- Conduct verification and testing of the silicon design.
Minimum qualifications:
- Bachelor’s degree in Electronics or Electrical Engineering, Physics, Computer Science, Computer Engineering, or a related field and 4 years of experience in the job offered or in a Silicon Engineer-related occupation.
- Alternatively, will accept a Master’s degree in Electronics or Electrical Engineering, Physics, Computer Science, Computer Engineering, or a related field and 2 years of experience in the job offered or in a Silicon Engineer-related occupation.
- Position requires: 2 years of experience in Computer processor architecture and processor microarchitecture; 2 years of experience in Object-oriented programming verification language (SystemVerilog, C++, or VHDL), and Constrained random verification; and 2 years of experience in Formal verification tools (Jasper or VC Formal), Simulation (VCS and Xcelium), Emulation (Cadence, Synopsys, and Siemens), or Post-silicon validation.
