Staff Architect, Onboard Compute Architecture

About the role

Muon Space is seeking a Staff Architect to define and evolve the end-to-end architecture of our onboard High Performance Compute (HPC) platform. You'll be the technical center of gravity across FPGA, GPU, CPU, and onboard networking, pulling together architectural threads from across the team and shaping a coherent, mission-flexible compute platform that will fly on Muon spacecraft for years to come.

You will work at the intersection of mission requirements, payload capabilities, and platform architecture, ensuring today's designs meet tomorrow's mission needs, and that our compute platform remains modular, configurable, and reusable across a growing fleet of missions.

This position is hybrid and requires working on-site in our San Jose, CA office three days per week.

Responsibilities

• Own the architecture process for Onboard High Performance Compute: how architectural decisions are proposed, discussed, documented, and ratified across the team and adjacent disciplines.
• Cluster and unify architectural concepts across the team into a coherent, documented, company-wide HPC architecture.
• Gather architectural requirements from across the company (payload, mission ops, program management, and future mission concepts) and translate them into a forward-looking compute roadmap.
• Own and evolve the technical roadmap for onboard high-performance compute, aligning architecture and timing against current and future missions.
• Drive cross-discipline architectural alignment across FPGA, GPU, and CPU compute and onboard networking; achieve consensus on data flows, processing pipelines, and compute partitioning.
• Champion a network-first onboard architecture with modular, configurable compute components that can be instantiated in mission-specific ways.
• Partner closely with the EE team to ensure architectural decisions are executable in silicon, PCB, and harness design.
• Stay ahead of upcoming mission needs and continuously evolve the technical line-up so mission objectives can be met without one-off architectures.
• Communicate architecture broadly through diagrams, design docs, white papers, and tech talks, so engineers, program managers, and leadership all share a common mental model of the platform.

Required Qualifications

• Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field, plus 7+ years of professional experience in system-level or compute-platform architecture.
• Proven track record architecting heterogeneous compute systems combining FPGA, GPU, and CPU elements, ideally in embedded, aerospace, or high-performance edge environments.
• Deep understanding of onboard networking and data-flow architectures, including Ethernet-based fabrics, DMA, zero-copy, and real-time streaming pipelines.
• Ability to balance architectural purity with mission pragmatism: designing for flexibility and reuse across many missions while shipping what today's missions need.
• Demonstrated experience driving cross-team architectural consensus across hardware, firmware, and software disciplines.
• Excellent written and verbal communication skills, including the ability to produce architecture documents and roadmap material for both technical and executive audiences.
• Ability and willingness to obtain and maintain a U.S. security clearance.

Nice-to-Have Skills

• Direct experience with spacecraft avionics, payload compute, or space-grade FPGA/GPU platforms.
• Familiarity with onboard networking standards relevant to space (e.g. Ethernet, SpaceWire).
• Prior experience defining modular, mission-configurable compute platforms or product families.
• Background in safety- or mission-critical development processes.
• Prior authorship of architectural white papers or public technical publications.

Salary

The salary range for this role is $210,000 - $234,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process.