Taiwan PCB Design Engineer TWN

Job Description

Role Purpose
The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client 
 

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• Review and contribute to schematics — understand circuit intent across power/precision supplies, ATE instrument (SMU / FVMI / FIMV) interfaces, high-speed MIPI, and control.
• Translate EE requirements into PCB design strategy — stackup, controlled impedance, PDN/decoupling, layer and reference-plane assignment, return-path planning, length/skew matching.
• Design for test scale-up — architect load boards, interface/slot boards, and pallets that scale from bring-up to high-volume manufacturing (dozens → hundreds of parallel sites) with correctness and reproducibility at scale.
• Own system-level SI & PI — impedance, PDN target-Z and anti-resonance, return-path integrity, and remote/Kelvin-sense loop stability across the full path (tester → cable → interface/slot board → pallet → socket → DUT), not just a single board. Includes IR-drop/PDN budgets, decoupling, crosstalk, and C-PHY/D-PHY routing.
• Drive suppliers and OSATs — author and own PCB constraints and layout direction; drive layout designers, PCB fab/CM suppliers, and OSAT/test houses to execute correctly; critically review their work and catch incomplete or wrong supplier "fixes."
• Design for deployment — ensure hardware is buildable, reproducible, and deployable across sites and geographies for HVM; drive DFM/DFA/DFT and material / REL-qual selection (thermal cycle, MSL, via reliability).
• Own end-to-end through HVM release — carry the design past layout handoff through bring-up, debug, bench correlation, and volume release; partner with ME on sockets, fixtures, mechanical integration, and EE↔ME tolerance stacks.
• Collaborate cross-functionally — with test, ME, silicon, and TPM; share design decisions transparently and participate in peer design reviews.

Work arrangement: primarily remote / work-from-home, with the ability to be on-site at the Asia lab (co-located with the OSAT / fab, e.g., Taiwan) during prototype bring-up and debug phases — hands-on lab work (scope, rework, characterization) happens on-site in Asia.

Travel: approximately 10% travel to OSAT / fab / test sites as needed

Language: Bilingual English – working proficiency ( communicate with customer & cross functional teams in US) & Mandarin

Skills

Must Have Skills:

• Proven schematic capture and review ability with solid analog/digital/power fundamentals, and the ability to translate EE requirements into a PCB design strategy. (Candence OrCAD / HDL , Allegro)
• Test / ATE hardware design — multi-site load boards, interface/slot boards, probe/socket interfaces. (Semiconductor test hardware is materially different from consumer PCB design.)
• PCB design in a professional EDA tool (Cadence Allegro / Constraint Manager or equivalent): stackup, controlled impedance, PDN, and system-level SI/PI.
• Strong working understanding of test scale-up (multi-site) and OSAT/deployability across the tester-to-DUT path.
• Demonstrated track record driving PCB fab / CM / assembly suppliers to correct execution.
• Exceptional cross-functional communication — tactfully push back on incomplete requirements or schematics, negotiate trade-offs with EE and ME, explain trade-offs clearly to non-PCB stakeholders, and firmly hold suppliers accountable (no DRC hacks).
• Hands-on in the lab — probes, reworks, and characterizes boards; proficient with high-speed oscilloscopes, DMMs, and power supplies, and comfortable with PCB rework/soldering for immediate prototype debug.
• Disciplined BOM and release management — respects PLM / version-control and issue-tracking processes (e.g., Agile / Arena / Teamcenter, Jira / Confluence, or equivalent).

Preferred Skills:

• Deep, independent ownership of cross-board, system-level scale-up strategy — sets design standards, resolves the hardest SI/PI, scale-up, and REL trade-offs.
• Proven OSAT engagement and HVM test-hardware deployment across sites/geographies at scale.
• Advanced SI/PI — PDN anti-resonance, return-path discontinuities, remote-sense loop stability — with tools (Sigrity / HFSS / TDR / VNA).
• High-speed serial (MIPI C-PHY / D-PHY), high-current / precision supply design.
• REL/qual and semiconductor test-flow (CP / FT) familiarity.