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Analog Devices·Semiconductors·18 hours ago
18 hours agoBe an early applicant

Digital Design (Physical) Engineer

Beijing, People's Republic of ChinaMid · 2-5 yearsDigital IC Design Engineer

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Must-have skills for this role

  • rtl-to-gdsii
  • physical design
  • static timing analysis
  • cadence innovus

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What you'll do

  • Contribute to the RTL-to-GDSII flow — floorplanning, power planning, placement, clock tree synthesis (CTS), and routing — with guidance from senior engineers
  • Run STA across PVT corners in multi-corner multi-mode (MCMM) setups and help resolve setup/hold violations with the design and layout teams
  • Support power delivery network (PDN) work, including IR-drop and electromigration (EM) analysis
  • Run DRC, LVS, antenna, and ERC checks and drive issues to clean signoff
  • Work with analog layout engineers on floorplan co-optimization and constraints at sensitive analog/digital boundaries
  • Support scan chain stitching and ATPG pattern generation
  • Script and automate repetitive physical design tasks to improve the team's flow
  • Support silicon bring-up and debug, correlating physical design decisions with lab measurements

What they're looking for

  • Solid understanding of digital logic, CMOS basics, and the IC design flow
  • Working understanding of static timing analysis, setup/hold, and clock domain crossing (CDC)
  • Coursework, internship, or tape-out project experience with digital implementation tools (Cadence Genus/Innovus/Tempus or an equivalent flow)
  • Ability to write Tcl, Python, or shell scripts to automate repetitive tasks
  • Careful, methodical approach to closure — able to track many small violations to zero without losing any
  • Strong collaboration with design and layout teams, and sufficient English for daily communication and technical documents

Nice to have

  • Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field
  • Tape-out experience from a university project or internship is a strong plus
  • Exposure to power analysis (IR-drop, EM) or power intent specification (UPF/CPF) is a plus
  • Exposure to DFT methodologies (scan insertion, compression, ATPG, JTAG/boundary scan) is a plus
  • Familiarity with both mature analog process nodes (e.g., 180nm BCD) and advanced digital nodes is a plus
  • Experience using AI tools to improve flow development or engineering productivity is a plus

Summarised by NextRaise from the employer’s description, which follows in full below.

Full description from employer

Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.


ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future. 


About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

          

Digital Design (Physical) Engineer


Position Summary


As a Digital Implementation (Physical Design) Engineer at Analog Devices, you will learn and contribute to the RTL-to-GDSII flow for digital and mixed-signal products. Working under the guidance of experienced engineers, you will take on floor planning, placement, clock tree synthesis, routing, and timing closure tasks on real production designs, and grow toward owning a block end to end.


Key Responsibilities

  • Physical Implementation: Contribute to the RTL-to-GDSII flow — floorplanning, power planning, placement, clock tree synthesis (CTS), and routing — with guidance from senior engineers
  • Static Timing Analysis: Run STA across PVT corners in multi-corner multi-mode (MCMM) setups and help resolve setup/hold violations with the design and layout teams
  • Power Integrity: Support power delivery network (PDN) work, including IR-drop and electromigration (EM) analysis
  • Physical Verification: Run DRC, LVS, antenna, and ERC checks and drive issues to clean signoff
  • Mixed-Signal Integration: Work with analog layout engineers on floorplan co-optimization and constraints at sensitive analog/digital boundaries
  • DFT: Support scan chain stitching and ATPG pattern generation
  • Flow and Automation: Script and automate repetitive physical design tasks to improve the team's flow
  • Silicon Support: Support silicon bring-up and debug, correlating physical design decisions with lab measurements

Requirements / Must Have Skills

  • Digital Design Fundamentals: Solid understanding of digital logic, CMOS basics, and the IC design flow
  • Timing Concepts: Working understanding of static timing analysis, setup/hold, and clock domain crossing (CDC)
  • EDA Exposure: Coursework, internship, or tape-out project experience with digital implementation tools (Cadence Genus/Innovus/Tempus or an equivalent flow)
  • Scripting: Ability to write Tcl, Python, or shell scripts to automate repetitive tasks
  • Engineering Rigor: Careful, methodical approach to closure — able to track many small violations to zero without losing any
  • Teamwork and English: Strong collaboration with design and layout teams, and sufficient English for daily communication and technical documents

Preferred Education and Experience

  • Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field
  • Tape-out experience from a university project or internship is a strong plus
  • Exposure to power analysis (IR-drop, EM) or power intent specification (UPF/CPF) is a plus
  • Exposure to DFT methodologies (scan insertion, compression, ATPG, JTAG/boundary scan) is a plus
  • Familiarity with both mature analog process nodes (e.g., 180nm BCD) and advanced digital nodes is a plus
  • Experience using AI tools to improve flow development or engineering productivity is a plus

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Graduate Job

          

Required Travel: No

          

Semiconductors

Company

Analog DevicesSemiconductors
Beijing, People's Republic of China

Company facts come from this company's own listings. We only show what the postings themselves carry.

Sourced from Analog Devices's careers site·first seen 22 Sept 2026·last verified 22 Sept 2026·How we source jobs

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