Firmware Architect
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What you'll do
- Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry)
- Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks
- Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry
- Lead silicon bring-up, partnering with ASIC design and signal integrity
- Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP)
- Partition HW-fixed vs. FW-adaptation (equalization, SNR monitoring)
- Travel: Up to 15% (silicon bring-up, standards meetings)
What they're looking for
- BS in Electrical Engineering, Computer Engineering, or Computer Science (MS preferred, DSP/comms focus)
- 8-10 years embedded firmware in high-speed SerDes/retimer products
- Hands-on PAM4 adaptation (LMS/CMA), FEC (KP4/RS-544)
- Silicon bring-up as lead (first samples to production)
- IEEE 802.3ck and 802.3dj link training experience
- RTOS (FreeRTOS/Zephyr) on constrained MCUs (1MB flash, 256KB RAM)
Nice to have
- MS in Electrical Engineering, Computer Engineering, or Computer Science (DSP/comms focus)
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
We are actively seeking a Firmware Architect either based in Hyderabad OR Bangalore.
Responsibilities:
- Define firmware architecture for 224G/lane AEC retimer (boot, config, calibration, link training, equalization, FEC, telemetry)
- Implement link training for IEEE 802.3ck (100G/lane) and 802.3dj (200G/lane), including adaptation algorithms and fallbacks
- Own FEC interaction (KP4, RS-544) and telemetry pipeline for Predictive Telemetry
- Lead silicon bring-up, partnering with ASIC design and signal integrity
- Ensure standards compliance (IEEE 802.3ck/dj, OIF-CEI, CMIS, OSFP)
- Partition HW-fixed vs. FW-adaptation (equalization, SNR monitoring)
- Travel: Up to 15% (silicon bring-up, standards meetings)
Skills:
- Good knowledge of C (C99, MISRA), assembly for critical paths, Python for tools
- Good knowledge of CI/CD, static analysis, hardware-in-loop tests
- Good understanding of standards implementation (IEEE 802.3, OIF)
- Good knowledge of SerDes architecture (equalization, telemetry, interrupts)
- Self-motivated, with strong sense of ownership and responsibility
- Good communication and reporting skills
Experience:
- Principal / Senior Staff (8-10 years post-degree)
- 8-10 years embedded firmware in high-speed SerDes/retimer products
- Hands-on PAM4 adaptation (LMS/CMA), FEC (KP4/RS-544)
- Silicon bring-up as lead (first samples to production)
- IEEE 802.3ck and 802.3dj link training experience
- RTOS (FreeRTOS/Zephyr) on constrained MCUs (1MB flash, 256KB RAM)
Education:
- BS in Electrical Engineering, Computer Engineering, or Computer Science (MS preferred, DSP/comms focus)
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It!
Company
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