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20 days ago
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Cadence Design Systems·Semiconductors·20 days ago
20 days ago

IC RTL2GDS Architect, AE

SAN JOSE, United States of AmericaSenior · 15+ yearsArchitect

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Must-have skills for this role

  • synthesis
  • p&r
  • sta
  • tcl

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About this role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Overview

The Architect will serve as a technical leader within Cadence’s North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions. This role demands exceptional technical depth, hands-on experience of design convergence, and the ability to align cross-functional teams toward delivering advanced design solutions for leading semiconductor companies.

Key Responsibilities

  • Technical Expertise: Lead technical engagements with customers and partners to achieve best-in-class PPA, working closely with design teams to meet customer success metrics, guiding adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes (3nm and below).
  • Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
  • Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure.
  • Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Qualifications

  • 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • Deep expertise in digital design fundamentals, advanced node implementation (3nm and below), and EDA tool ecosystems.
  • Proven track record of leading technical teams and driving customer success at executive levels.
  • Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
  • Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
  • Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and competitive solutions highly desirable.

The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Semiconductors

Company

Cadence Design SystemsSemiconductors
SAN JOSE, United States of America

Company facts come from this company's own listings. We only show what the postings themselves carry.

Sourced from Cadence Design Systems's careers site·first seen 26 May 2026·last verified 8 Sept 2026·How we source jobs

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