Cisco·4 days ago
4 days ago
Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years
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What you'll do
- Drive high-performance ASIC design verification for Cisco's enterprise platforms
- Lead teams in defining and verifying ASICs
- Collaborate cross-functionally
- Ensure quality delivery
What they're looking for
- 15+ years of experience in ASIC design verification
- Strong technical leadership
- Expertise in UVM, C++, and ASIC development
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
We are recruiting an ASIC Design Verification Engineering Leader to drive high-performance ASIC design verification for Cisco's enterprise platforms. Lead teams in defining and verifying ASICs, collaborate cross-functionally, and ensure quality delivery. Ideal for experienced ASIC engineers with strong technical leadership and expertise in UVM, C++, and ASIC development.
Skills
- system validation
- code review
- dv architecture strategy
- code coverage analysis
- mentoring
- system simulation
- eve
- asic design verification
- team leadership
- debugging
- makefiles
- postmortem analysis
- asic/soc development cycle
- test plan review
- veloce
- uvm methodology
- c++
- testbench development
- rtl verification
- system verilog
- flow automation
- c/c++ programming
- hardware bring-up
Company
Cisco
Bengaluru, India
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