NextRaiseNextRaiseFind jobs
Sign inSign up free
Jobs / Digital IC Design Engineer in United States of America
5 months ago
Apply with autofill
Apply with autofill
Etched·5 months ago
5 months ago

Physical Design Engineer

Austin, United States of AmericaFull-timeOn-siteSenior · 5-10 years₹1.7Cr – ₹2.5Cr/yr · est.Digital IC Design Engineer

Sign up free to see how well your resume matches this role.

Boost your chances at etched

How you compare FREE

?
Your scoreYour score: not yet known
→
66
Top 10%Top 10%: 66 out of 100

Top 10% of NextRaise users matched against Digital IC Design Engineer roles in United States.

PDF or DOCX · no account needed

Apply faster with autofill FREEetched uses Ashby - autofill it instead of retyping.careers.example.com/applyAutofillingFull namePriya SharmaEmailpriya.sharma@example.comPhone+49 30 1234567LocationBerlGet the extension

About this role

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.


Key Responsibilities

  • Deeply understand what is involved in physical design

  • Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
    improve CAD infrastructure

  • Collaborate with RTL Designers and provide Physical Design feedback to improve PPA

  • Drive dashboards that show the convergence of projects related to PD

  • Optimize tool flows, working with EDA vendors to incorporate the latest features

  • Accountable for block level closure

  • Supervise the outsourcing of physical design to a 3rd party service

You may be a good fit if you have

  • 5-10+ years of previous experience with PD

  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off

  • Experience with back-end design and timing closure on advanced process nodes (5nm
    and below)

  • Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
    automated RTL-to-GDSII flows

  • Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)

  • Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
    routing, IR drop, and EM/antenna analysis

  • Deeply creative and able to think from first principles

Strong candidates may also have experience with

  • Familiarity with modern ML and LLM model architectures

  • Ability to program with Python or another scripting language

  • Familiarity with AI tools for programming/coding

  • Startup experience or comfort working in fast-paced environments

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch + dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

Company

Etched
Austin, United States of America

Company facts come from this company's own listings. We only show what the postings themselves carry.

Sourced from Etched's careers site·first seen 16 Jun 2026·last verified 8 Sept 2026·How we source jobs

Similar jobs

  • VLSI Engineer II Graduate at HPE (Hewlett Packard Enterprise)Sunnyvale, United States of America–match not yet calculated
  • VLSI Engineer I Graduate at HPE (Hewlett Packard Enterprise)Sunnyvale, United States of America–match not yet calculated
  • Intern – DRAM Technology Physical Design and Block-Level PPA Optimization at Micron TechnologyBoise, United States of America–match not yet calculated
  • Digital IC Design Intern, MS - Summer 2027 at MarvellSanta Clara, United States of America–match not yet calculated
  • Physical Design Lead — Execution at alteraSan Jose, United States of America–match not yet calculated

Browse more jobs

  • Digital IC Design Engineer jobs in United States
  • IC Verification Engineer jobs in United States
  • Analog IC Design Engineer jobs in United States
  • Process / Device Engineer jobs in United States
  • Digital IC Design Engineer jobs in India
  • Digital IC Design Engineer jobs in Canada