Senior RTL Design and Integration Engineer, Google Cloud
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What you'll do
- Participate in Design, implementation and integration of chassis, subsystems and SoC. Technology migration of Standard, foundational and Third-Party Intellectual Property (3PIPs).
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks and quality check flows like Lint, CDC, RDC, VCLP.
- Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Coordinate with various IP teams to meet schedule and quality requirements.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- 8 years of experience in design, implementation and integration of chassis, subsystems and SoC.
- Experience with logic synthesis for RTL code, performance, and power.
- Experience with low-power design.
Nice to have
- Master's degree or PhD in Electrical Engineering or Computer Science or equivalent practical experience with 10 years of relevant industry experience.
- Experience in owning medium complex SoC integration and QC.
- Experience with scripting languages (e.g., Python or Perl).
- Experience with tape outs and bring up (support).
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
- Good understanding of Verilog or System verilog language.
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will join a team developing Application-Specific Integrated Circuits (ASICs) to accelerate machine learning computation in data centers. You will collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to specify and deliver quality designs for next-generation accelerators. You will solve technical problems through micro-architecture innovation and evaluate design trade-offs between performance and power.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities:
- Participate in Design, implementation and integration of chassis, subsystems and SoC. Technology migration of Standard, foundational and Third-Party Intellectual Property (3PIPs).
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks and quality check flows like Lint, CDC, RDC, VCLP.
- Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Coordinate with various IP teams to meet schedule and quality requirements.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- 8 years of experience in design, implementation and integration of chassis, subsystems and SoC.
- Experience with logic synthesis for RTL code, performance, and power.
- Experience with low-power design.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science or equivalent practical experience with 10 years of relevant industry experience.
- Experience in owning medium complex SoC integration and QC.
- Experience with scripting languages (e.g., Python or Perl).
- Experience with tape outs and bring up (support).
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
- Good understanding of Verilog or System verilog language.
Company
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