Silicon Validation Engineer, Memory Subsystem, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Silicon Validation Engineer, you will be part of Google’s Consumer Hardware Silicon team, developing high performance and low power hardware to enable Google’s continuous innovations in this space. You will be a key member of the cross-functional memory sub-system silicon validation team responsible for ensuring that we deliver high-quality silicon to all internal customers, thereby providing differentiating customer experiences. You will plan, write and execute tests to establish the functional health of our System on Chips (SoCs) on emulation and on silicon, both under nominal and process, voltage, and temperature (PVT) conditions. You will contribute to the laboratory debug of failures with cross-functional teams (e.g., Silicon, Boards, Software, Manufacturing). You will measure and optimize performance and power of silicon, enabling consistent and compelling use-cases in our end-products. You will provide regular updates about Silicon health to platform, software and volume manufacturing teams.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities:

• Work with Architecture, Design and product teams to understand requirements for memory subsystem validation (e.g., double data rate physical layer (DDRPHY), Memory Controller, dynamic random-access memory (DRAM)).
• Understand the design and develop/execute validation tests to establish functionality of new design on emulation platform for tapeout for DDRPHY and DRAM subsystem.
• Drive the post silicon bringup and validation activities for the DDRPHY/DRAM interface including its tuning and characterization.
• Develop various post silicon validation/debug/margin tools related to DDRPHY and DRAM.
• Provide regular updates about Emulation/Silicon health to platform, software and volume manufacturing teams.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in silicon validation.
• Experience with DDRPHY and DRAM tuning and characterization over PVT.
• Experience in developing test and debug infrastructure (e.g., software tools, lab equipment) and test/lab automation scripting.
• Experience with low power DRAM interface protocols and compliance.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Familiarity with Prototyping platforms like Emulators or Field Programmable Gate Array (FPGAs).
• Familiarity with power or performance measurement of SoCs.
• C/Python Coding experience.