Sr. Module Engineer, Hybrid Bonding
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What you'll do
- Develop and optimize die-to-wafer (D2W) hybrid bonding processes for advanced packaging applications.
- Establish process windows for surface preparation, plasma activation, die placement, alignment and overlay control, bonding temperature and pressure optimization, and post-bond annealing.
- Drive Cu-Cu and dielectric-dielectric interconnect formation with focus on electrical performance and reliability.
- Support integration of hybrid bonding into memory architectures, chiplet-based systems, silicon interposers, system-on-wafer platforms, and co-packaged optics (CPO).
- Collaborate with integration teams to resolve process interactions and yield excursions.
- Identify root causes of bond voids, die shift, overlay errors, non-uniform bonding, and particle contamination.
- Utilize DOE methodologies and statistical process control to improve yield and process robustness.
- Drive bonding quality characterization using CSAM, X-ray inspection, FIB/SEM, AFM, optical metrology, and electrical test structures.
- Develop correlation between process parameters and package performance.
- Work closely with equipment engineering teams on hybrid bonding systems, die placement tools, plasma activation modules, surface preparation modules, and integrated process control solutions.
- Participate in evaluation and qualification of next-generation bonding platforms.
- Define and execute reliability test plans including thermal cycling, HTOL, mechanical pull/shear testing, and moisture sensitivity evaluations.
What they're looking for
- M.S. or Ph.D. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, Physics, or Semiconductor Manufacturing
- Minimum 5+ years of semiconductor process development experience after graduate degree
- Direct experience in at least one of the following: Hybrid bonding, Thermocompression bonding, Wafer bonding, Advanced packaging, HBM development, Cu interconnect technology, Chiplet integration
- Strong understanding of Cu-Cu interconnect formation, Surface chemistry and plasma activation, CMP and planarization, Defect engineering, Semiconductor process integration, Statistical process analysis
- Experience with DOE and JMP/Minitab analysis tools
- Familiarity with metrology and failure analysis techniques
Nice to have
- Ph.D. with 5+ years industry experience
- Experience in HBM or 3D stacking technologies
- Experience with Hybrid bonding equipment development, Direct bonding interconnect (DBI), Die placement systems, Advanced packaging process integration
- Knowledge of AI/HPC packaging architectures
- Experience working with 200 mm and 300 mm wafer manufacturing environments
- Track record of patents, publications, or conference presentations (ECTC, IEEE, IMAPS, SEMI, etc.)
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
Who We Are
Applied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.
What We Offer
Salary:
$147,000.00 - $202,500.00Location:
Santa Clara,CAYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more.
At Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits.
As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies. You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.
Position Summary
We are seeking a highly motivated Die-to-Wafer Hybrid Bonding Module Engineer to develop and scale next-generation hybrid bonding technologies for advanced semiconductor packaging applications including Memory, chiplets, AI accelerators, photonics, and heterogeneous integration platforms.
The successful candidate will lead process module development across die preparation, surface activation, die placement, hybrid bonding, post-bond characterization, yield improvement, and manufacturing scale-up. This role requires close collaboration with equipment development teams, process integration engineers, materials scientists, device architects, and external ecosystem partners.
The position is ideal for candidates passionate about enabling future high-bandwidth and energy-efficient computing systems through advanced interconnect technologies. Hybrid bonding technologies including copper-copper and dielectric-dielectric direct bonding are critical enablers for next-generation 3D integration and HBM stacking.
Key Responsibilities
Hybrid Bonding Process Development
- Develop and optimize die-to-wafer (D2W) hybrid bonding processes for advanced packaging applications.
- Establish process windows for:
- Surface preparation
- Plasma activation
- Die placement
- Alignment and overlay control
- Bonding temperature and pressure optimization
- Post-bond annealing
- Drive Cu-Cu and dielectric-dielectric interconnect formation with focus on electrical performance and reliability.
Process Integration
- Support integration of hybrid bonding into:
- Memory architectures
- Chiplet-based systems
- Silicon interposers
- System-on-Wafer platforms
- Co-packaged optics (CPO)
- Collaborate with integration teams to resolve process interactions and yield excursions.
Yield and Defect Reduction
- Identify root causes of:
- Bond voids
- Die shift
- Overlay errors
- Non-uniform bonding
- Particle contamination
- Utilize DOE methodologies and statistical process control to improve yield and process robustness.
Metrology and Characterization
- Drive bonding quality characterization using:
- CSAM
- X-ray inspection
- FIB/SEM
- AFM
- Optical metrology
- Electrical test structures
- Develop correlation between process parameters and package performance.
Equipment and Technology Development
- Work closely with equipment engineering teams on:
- Hybrid bonding systems
- Die placement tools
- Plasma activation modules
- Surface preparation modules
- Integrated process control solutions
- Participate in evaluation and qualification of next-generation bonding platforms.
Reliability Engineering
- Define and execute reliability test plans:
- Thermal cycling
- HTOL
- Mechanical pull/shear testing
- Moisture sensitivity evaluations
- Drive failure analysis and corrective actions.
Technical Leadership
- Lead cross-functional projects from concept through technology transfer.
- Publish technical results internally and externally.
- Present development progress to engineering leadership and customers.
- Mentor junior engineers and researchers.
- Minimum Qualifications
Education
- M.S. in:
- Materials Science
- Electrical Engineering
- Mechanical Engineering
- Chemical Engineering
- Physics
- Semiconductor Manufacturing
- OR
- Ph.D. in one of the above disciplines
Experience
- Minimum 5+ years of semiconductor process development experience after graduate degree.
- Direct experience in at least one of the following:
- Hybrid bonding
- Thermocompression bonding
- Wafer bonding
- Advanced packaging
- HBM development
- Cu interconnect technology
- Chiplet integration
Technical Skills
- Strong understanding of:
- Cu-Cu interconnect formation
- Surface chemistry and plasma activation
- CMP and planarization
- Defect engineering
- Semiconductor process integration
- Statistical process analysis
- Experience with DOE and JMP/Minitab analysis tools.
- Familiarity with metrology and failure analysis techniques.
Preferred Qualifications
- Ph.D. with 5+ years industry experience.
- Experience in HBM or 3D stacking technologies.
- Experience with:
- Hybrid bonding equipment development
- Direct bonding interconnect (DBI)
- Die placement systems
- Advanced packaging process integration
- Knowledge of AI/HPC packaging architectures.
- Experience working with 200 mm and 300 mm wafer manufacturing environments.
- Track record of patents, publications, or conference presentations (ECTC, IEEE, IMAPS, SEMI, etc.).
Desired Personal Attributes
- Strong technical leadership.
- Excellent problem-solving skills.
- Hands-on laboratory mindset.
- Ability to drive technology from R&D into manufacturing.
- Effective communicator across engineering, operations, and customer-facing teams.
- Passion for enabling next-generation AI and high-performance computing platforms.
- M.S. in:
Additional Information
Time Type:
Full timeEmployee Type:
Assignee / RegularTravel:
Yes, 10% of the TimeRelocation Eligible:
YesThe salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable.
For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement.
Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.
In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.
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