Staff Analog Design Engineer
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What you'll do
- Lead technical feasibility of innovative architectures for IP macro-blocks within Power ICs, i.e. power-stages, gate drivers and various sub-systems.
- Explore, compare and derive KPIs and achievable specs for various architectural and process technology options by means of mathematical/prediction models, circuit models, existing designs and/or lab evaluation data.
- Hands-on custom design of analogue/mixed-signal IP macro-blocks in planar and FinFET technologies.
- Lead and own design, pre- and post-layout verification (block- and top-level), spec compliance matrix, behavioural modelling, layout implementation, and documentation.
- Provide guidance, reviews and CAPA to IP-level floorplan and layout implementation of analogue/mixed-signal blocks.
- Run layout parasitic extraction and post-layout back-annotated simulations.
- Interface to the IC Design Lead and development teams to enable smooth IP integration into IC top-level.
- Interface with engineering teams outside analogue design for what matters to the IP macro-blocks being responsible for.
- Support the lab evaluation team and/or take ownership of silicon lab validation of the designed IP macroblocks as required.
- Support test engineering and operation teams for product characterisation and qualification.
- Coordinate tasks of junior colleagues or external sub-cons: distribute, monitor, review, and improve quality.
What they're looking for
- MS in Electrical Engineering with 5+ years' experience in power IC design or 8-12 years in analogue/mixed-signal IC design.
- Expert-level proficiency with Cadence Virtuoso and simulation
- Strong understanding of analogue/mixed-signal design and layout techniques: CMOS process technology manufacturing, offset, noise, efficiency, current density, ESD, reliability, test & trim, thermals.
- Strong sense of ownership/accountability; able to work independently and collaboratively in a team environment, including cross-site collaboration (i.e. US and other locations).
- Experience with hands-on parasitic analysis, post-layout circuit simulation and parasitic optimization
- Excellent communication skills (verbal, written) with the ability to present complex technical topics using simple and effective communication when needed, as well as the ability to deep-dive into technical details if required.
Nice to have
- Experience in lab silicon validation of IPs within PMIC / Power ICs is desirable
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
Staff Analog Design Engineer, Data Center & Energy, IVR Technology
About the Role
As a Staff Analog Design Engineer at Analog Devices, you will lead the design and development of complex analog and mixed-signal integrated circuits, working with significant latitude to solve challenging technical problems. You'll provide technical leadership on critical projects, contribute to architectural decisions, and mentor less experienced engineers while collaborating with cross-functional teams. This role requires deep technical expertise combined with broader business understanding to drive innovation and ensure successful product delivery across multiple applications and markets.
Role Overview
To expand the team in Munich we are seeking an experienced Analog Design Engineer to contribute to the development of high-performance power management ICs in advanced CMOS nodes. In this role, you will collaborate closely with a team of circuit designers to deliver high-density, ultra efficient circuit implementations that meet aggressive performance and size targets.
The ideal candidate has 10+ years of hands-on experience in analog IC design (or 5+ years’ experience in Power IC and DC/DC design), deep expertise in custom IC development flows from definition to layout and silicon evaluation, and thrives in a startup-like, high-accountability culture.
Key Responsibilities
- LeadtechnicalfeasibilityofinnovativearchitecturesforIPmacro-blockswithinPowerICs,i.e.power-stages, gate drivers and various sub-systems (control, diagnostics, monitoring, telemetry, voltage/current/timing references, internal supplies, etc). Explore, compare and derive KPIs and achievable specs for various architectural and process technology options by means of mathematical/prediction models, circuit models, existing designs and/or lab evaluation data.
- Hands-on custom design of analogue/mixed-signal IP macro-blocks in planar and FinFET technologies. Lead and own design, pre- and post-layout verification (block- and top-level), spec compliance matrix, behavioural modelling, layout implementation, and documentation.
- Provide guidance, reviews and CAPA to IP-level floorplan and layout implementation of analogue/mixed-signal blocks, with attention to matching, shielding, routing, parasitic, electromigration, DFM, area optimization, etc.
- Run layout parasitic extraction and post-layout back-annotated simulations.
- Interface to the IC Design Lead and development teams to enable smooth IPintegration into IC top-level
- Interface with engineering teams outside analogue design (i.e., passive design, package design, digital design, verification) for what matters to the IP macro-blocks being responsible for.
- Support the lab evaluation team and/or take ownership of silicon lab validation of the designed IP macroblocks as required.
- Support test engineering and operation teams for product characterisation and qualification.
- Coordinate tasks of junior colleagues or external sub-cons: distribute, monitor, review, and improve quality of
Qualifications:
- MS in Electrical Engineering with 5+ years' experience in power IC design or 8-12 years in analogue/mixed-signal IC design.
- Expert-level proficiency with Cadence Virtuoso and simulation
- Strong understanding of analogue/mixed-signal design and layout techniques: CMOS process technology manufacturing, offset, noise, efficiency, current density, ESD, reliability, test & trim, thermals.
- Strong sense of ownership/accountability; able to work independently and collaboratively in a team environment, including cross-site collaboration (i.e. US and other locations).
- Experiencewithhands-onparasiticanalysis,post-layoutcircuitsimulationandparasiticoptimizationis
- Excellent communication skills (verbal, written) with the ability to present complex technical topics using simple and effective communication when needed, as well as the ability to deep-dive into technical details if required.
- Experience in lab silicon validation of IPs within PMIC / Power ICs is desirable
#LI-EC1
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
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