ASIC Engineer || Physical Design | Floor Planning | GSP & PD | Exp - 8 to 11 years
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What you'll do
- Involved in creating next generation state-of-the-art networking chips in advanced process node.
- Drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
What they're looking for
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with 8+ Years of exp
- All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Hierarchical design implementation approach, Timing closure, physical convergence.
- Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions.Power Integrity Analysis.
- STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
- Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
Nice to have
- Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
- Good understanding of different CTS strategies and providing the feedback to Implementation Team.
- As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work.
- Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
Meet the Team :
Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!
Your Impact :
Our creative and talented Physical Design team in Bangalore, India. As a member of this team, you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
Minimum Qualifications :
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with 8+ Years of exp
All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
Hierarchical design implementation approach, Timing closure, physical convergence.
Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions.Power Integrity Analysis.
STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
Preferred Qualifications :
Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
Good understanding of different CTS strategies and providing the feedback to Implementation Team.
As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work.
Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
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