Cisco·10 days ago
10 days ago
ASIC Engineering Technical Leader || Physical Design | Floor Planning | GSP & PD | Exp - 11+ years
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What you'll do
- Drive next-generation networking chip development as an ASIC Engineering Technical Leader in Physical Design
- Lead the RTL 2 GDS implementation, focusing on floor planning, place & route, and performance optimisation
What they're looking for
- 11+ years of experience in ASIC engineering with deep expertise in advanced process nodes and large-scale design
- Expertise in RTL 2 GDS implementation, focusing on floor planning, place & route, and performance optimisation
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
Become part of our team as an ASIC Engineering Technical Leader in Physical Design, driving next-generation networking chip development. Lead the RTL 2 GDS implementation, focusing on floor planning, place & route, and performance optimisation. Ideal for experienced ASIC engineers with deep expertise in advanced process nodes and large-scale design.
Skills
- asic physical implementation
- floor planning
- tcl
- clock and power distribution
- global signal planning
- hierarchical design implementation
- i/o planning
- hard ip integration
- timing closure
- physical convergence
- power integrity analysis
- eda tools
- synopsys dc/fc
- synopsys formality
- cadence innovus
- synopsys icc2
- mentor calibre
- primetime-dmsa
- apache redhawk
- synopsys icv
- synopsys lec
- static timing verification
- power integrity
- debugging
- python
- shell
- perl
- design for yield
- manufacturability
- multi-vt strategies
Company
Cisco
Bengaluru, India
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