IP RTL Design Engineer

Job Details:

Job Description: 

Role and Impact:

As a Component IP RTL Design Engineer for Intel Unified Chassis, you will be responsible for developing, implementing, and supporting a variety of IP components, with a major focus on protocol bridges. In this role, you will collaborate with architects and senior engineers to define, design, and validate protocol bridge solutions, as well as other IP blocks as required for Unified Intel Chassis designs. Your primary work will involve protocol conversion, access control, and error handling across interfaces such as AXI, AXI-Lite, APB, IOSF-SB, HBW, and LBW, but you may also contribute to other IP development, integration, and debug activities to meet system-level requirements and quality standards.

Key Responsibilities:

• Design, implement, and verify protocol bridges between different bus and interconnect standards (e.g., AXI, AXI-Lite, APB, IOSF-SB, HBW, LBW).
• Contribute to the development and support of other IP components as needed for Intel Chassis projects.
• Collaborate with architects and senior engineers to define microarchitecture and interface requirements for protocol bridges and other IP blocks.
• Develop RTL code and simulations for protocol bridge logic and other IP, ensuring functional correctness and performance targets.
• Implement access control, privilege qualification, and policy propagation for secure data paths.
• Support error detection, parity/ECC generation and checking, and transaction error handling in protocol bridges and other IP.
• Assist in integration, verification, and debug of protocol bridges and other IP within larger IP or SoC environments.
• Document design features, test plans, and results for protocol bridge and other IP deliverables.
• Work with validation, firmware, and post-silicon teams to ensure IP functionality and diagnosability.
• Contribute to compliance with quality assurance standards and smooth handoff of IP deliverables.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in electrical engineering, Computer Engineering, or related field.
• Minimum 6-15 years of experience in RTL coding, logic design, and simulation.
• Proficiency in hardware description languages such as Verilog or VHDL.
• Strong knowledge of digital design principles, including power, performance, and area optimization.
• Familiarity with tools for synthesis, timing analysis, and formal verification.
• Experience with debugging RTL and resolving failing tests.
• .Expertise in RAS/debug/security/telemetry

Preferred Qualifications:

• Master's or PhD in Electrical Engineering, Computer Engineering, or related field.
• Strong communication and collaboration skills to work effectively in a cross-functional team environment.
• Experience in supporting SoC customers with IP integration and verification.
• Knowledge of industry trends and emerging technologies in logic design and chip development.
• Proven ability to lead projects and provide innovative solutions to complex technical challenges.
• NOC in IP Design, Credit-Based Fabric & Bridge Architectures, High-Throughput SoC Interconnect Design, Fabric / Protocol IP, Scalable Interconnect .

Join us at Intel and become part of a team where your engineering expertise will shape the future of cutting-edge technologies. Apply today to drive innovation and make an impact.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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