Senior RTL Design Engineer - CPU & Microarchitecture

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟮𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟮𝟱𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟮-𝟮𝟱 𝗟𝗣𝗔)

Experience: 5+ yrs

Location: Bengaluru, Hyderabad, Telangana, India

Job Type: Full-time

We are looking for an experienced Senior RTL Design Engineer – CPU & Microarchitecture to contribute to the design and development of high-performance ASIC and SoC architectures, with a strong focus on CPU cores and processor subsystems.

The ideal candidate will have deep expertise in RTL design, SystemVerilog, CPU microarchitecture, and computer organization, along with practical experience developing complex digital designs for production silicon. You will contribute to architecture implementation, RTL development, verification collaboration, synthesis readiness, and technical debugging across the SoC development lifecycle.

Requirements

KEY RESPONSIBILITIES

• Design, develop, and maintain synthesizable RTL for CPU cores and processor subsystems.
• Translate CPU microarchitecture specifications into efficient and scalable RTL implementations.
• Develop and optimise instruction execution pipelines, hazard handling, branch prediction, and related CPU datapath/control logic.
• Design and integrate L1/L2 cache, MMU, interrupt, and memory subsystem components.
• Implement and integrate AMBA-based interfaces and interconnect protocols including AXI, AHB, APB, ACE, and CHI.
• Develop high-quality RTL using SystemVerilog, Verilog, and VHDL.
• Participate in microarchitecture reviews, RTL design reviews, and technical design discussions.
• Perform RTL linting, structural analysis, and front-end quality checks using tools such as Synopsys SpyGlass and VCS.
• Support synthesis and design implementation activities using Synopsys Design Compiler or Cadence Genus.
• Collaborate with verification engineers to support functional verification, debug, and design quality.
• Analyse simulation results, identify RTL issues, and drive root-cause resolution.
• Develop scripts and automation using Python, Perl, TCL, Bash, or similar scripting languages.
• Support FPGA prototyping and hardware validation activities where required.
• Contribute to post-silicon bring-up, debugging, and issue resolution.
• Support performance, power, area, and timing optimisation of CPU and SoC designs.
• Apply appropriate low-power design techniques where required.
• Maintain technical documentation related to RTL, microarchitecture, interfaces, and design decisions.
• Collaborate with architecture, verification, physical design, validation, and system teams throughout the development lifecycle.
• Mentor junior engineers and contribute to RTL design standards and best practices.

WHAT MAKES YOU A GREAT FIT

• 5+ years of experience in ASIC/SoC RTL design, including at least 2+ years of dedicated experience in CPU core or processor subsystem RTL design.
• Strong hands-on expertise in SystemVerilog, Verilog, and VHDL.
• Strong understanding of CPU microarchitecture and computer organization.
• Practical knowledge of instruction pipelines, hazard handling, branch prediction, L1/L2 caches, MMU, interrupts, and processor subsystems.
• Strong experience with AMBA protocols, particularly AXI, AHB, APB, ACE, and CHI.
• Hands-on experience with front-end EDA tools such as Synopsys SpyGlass, VCS, Design Compiler, Cadence Genus, or Xcelium.
• Strong scripting and automation skills using Python, Perl, TCL, Bash, or equivalent.
• Experience with at least one processor architecture such as RISC-V, ARM, x86, or proprietary CPU architectures is preferred.
• Understanding of RTL synthesis, timing considerations, design quality, and ASIC/SoC development flows.
• Exposure to low-power design methodologies is an advantage.
• Experience with FPGA prototyping, post-silicon bring-up, and hardware debugging is desirable.
• Knowledge of assembly programming and processor instruction sets is an advantage.
• Strong debugging, analytical, and problem-solving skills.
• Ability to work effectively with architecture, verification, physical design, and validation teams.
• Strong understanding of digital design principles and RTL coding best practices.
• Excellent communication and technical documentation skills.
• Ability to take ownership of complex design problems and deliver high-quality solutions within project timelines.
• B.Tech/M.Tech in Electronics, VLSI, Microelectronics, Computer Engineering, or a related discipline is preferred.