Celerocommunicationsinc·4 days ago
4 days ago
Principal DFT Engineer
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What you'll do
- Develop and implement DFT architecture for ASIC and SoC designs.
- Perform scan insertion, scan chain planning, and scan compression implementation.
- Generate and validate ATPG patterns and analyze fault coverage results.
- Implement and verify MBIST, and other on-chip test features.
- Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
- Support JTAG and boundary-scan implementation and debug.
- Drive DFT signoff activities and manufacturing test readiness.
- Participate in silicon bring-up, failure analysis, and yield improvement efforts.
What they're looking for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of ASIC/SoC DFT experience.
- Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
- Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
- Knowledge of Verilog/SystemVerilog and digital design fundamentals.
- Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
- Results-driven engineer with strong debugging abilities.
- Comfortable working in fast-paced cross-functional environments.
- Passion for delivering high-quality silicon products.
Nice to have
- Experience with advanced-node semiconductor technologies.
- Hands-on experience with MBIST, compression architectures, and JTAG.
- Knowledge of timing closure, physical design impacts, and low-power design techniques.
- Experience supporting silicon validation and manufacturing production ramps.
- Strong communication and cross-functional collaboration skills.
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.
What You Will Do
- Develop and implement DFT architecture for ASIC and SoC designs.
- Perform scan insertion, scan chain planning, and scan compression implementation.
- Generate and validate ATPG patterns and analyze fault coverage results.
- Implement and verify MBIST, and other on-chip test features.
- Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
- Support JTAG and boundary-scan implementation and debug.
- Drive DFT signoff activities and manufacturing test readiness.
- Participate in silicon bring-up, failure analysis, and yield improvement efforts.
What You Will Bring
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of ASIC/SoC DFT experience.
- Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
- Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
- Knowledge of Verilog/SystemVerilog and digital design fundamentals.
- Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
- Results-driven engineer with strong debugging abilities.
- Comfortable working in fast-paced cross-functional environments.
- Passion for delivering high-quality silicon products.
Preferred Qualifications
- Experience with advanced-node semiconductor technologies.
- Hands-on experience with MBIST, compression architectures, and JTAG.
- Knowledge of timing closure, physical design impacts, and low-power design techniques.
- Experience supporting silicon validation and manufacturing production ramps.
- Strong communication and cross-functional collaboration skills.
Annual Base Salary Range for US: $200,000 - $240,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
Company
Celerocommunicationsinc
Irvine, United States of America
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