Senior ASIC Design Verification Engineer - Slingshot

Senior ASIC Design Verification Engineer - Slingshot

  

This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.

Job Description:

   

This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. In this case, Chippewa Falls, WI, Fort Collins, CO or Bloomington, MN.

Who We Are

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

About the Team and the Project

Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems (https://www.hpe.com/us/en/compute/hpc/slingshot-interconnect.html).

As a Senior Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own significant verification scope, set technical direction for a block or subsystem, and help shape how our team applies emerging agentic AI workflows to solve complex engineering problems.

We are looking for engineers who want to work at the leading edge of high-performance interconnects for HPC and AI, who enjoy mentoring, and who want real influence over verification methodology rather than a narrowly defined test-writing role.

Job Description

In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews.

Responsibilities

• Follow and help define the team's design verification methodology.

• Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.

• Plan and implement block and integration level scoreboards and checkers to verify functional behavior.

• Write and analyze functional coverage, providing input to block level milestones.

• Triage regression failures and identify logic bugs, while driving bug closure.

• Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.

• Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.

• Participate in and provide input on the process for selection of future technical leaders.

• Drive VLSI innovation and integration of new technologies into projects and activities in the design organization.

Education and Experience Required

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.

• 10+ years of experience in VLSI design, verification, or implementation.

Knowledge and Skills

• Expert level knowledge of SystemVerilog and of OVM or UVM methodologies.

• Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.

• Expert level analytical and problem solving skills.

• Ability to excel in a distributed team environment.

• Executive level written and verbal communication skills; mastery in English.

Preferred Skills

• Experience verifying high-speed networking, switching, or NIC ASICs.

• Experience with agentic AI coding tools and workflows applied to verification.

• Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.

• Experience working as part of a geographically distributed team.

Accessibility

HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.

Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Job:

Engineering

Job Level:

TCP_04

    

"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 142,000 - 270,000 in Colorado // 135,000 - 310,500 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

The estimated job application period closure is October 1 2026; this timeline is provided for transparency and internal planning purposes.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

   

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

   

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All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.