Tech Lead, Physical Design
Sign up free to see how well your resume matches this role.
What you'll do
- Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
- Support or develop complex SoC/silicon products for Server, Storage, and/or Networking applications.
What they're looking for
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
- ≥6 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.
- Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
- Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
- Experience with Cadence and/or Synopsys physical design tools/flows.
- Familiarity and working knowledge of System Verilog/Verilog.
- Experience with DFT tools and techniques.
- Experience in working with IP vendors for both RTL and hard-mac blocks.
- Good scripting skills in python or Perl
Nice to have
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
- Familiarity with DFT test coverage and debug.
- Familiarity with ECO methodologies and tools.
Summarised by NextRaise from the employer’s description, which follows in full below.
Full description from employer
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Tech Lead Physical Design
Experience - 6-14 years
Bengaluru, India
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
What You’ll Do
- Own and execute end-to-end physical design implementation for complex, high-performance ASIC/SoC designs.
- Work on physical design activities including:
- Floorplanning and partitioning
- Power planning
- Placement and optimization
- Clock Tree Synthesis (CTS)
- Routing and post-route optimization
- Timing closure
- Physical verification
- ECO implementation
- Perform Static Timing Analysis (STA) and resolve setup/hold timing violations.
- Analyze and address congestion, IR drop, electromigration, signal integrity, and other physical design challenges.
- Work closely with RTL, Design Verification, DFT, STA, and architecture teams to ensure successful design implementation.
- Drive PPA optimization while meeting aggressive timing and power targets.
- Participate in design signoff activities and ensure the design meets required timing, power, and physical verification criteria.
- Develop and maintain automation scripts and flows to improve physical design productivity.
- Debug complex implementation issues and contribute to improving physical design methodologies and flows.
Required Qualifications
- Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.
- Strong understanding of ASIC physical design flows and methodologies.
- Hands-on experience with physical design implementation from netlist to GDSII.
- Good understanding of:
- Floorplanning
- Placement
- CTS
- Routing
- STA
- Timing closure
- Physical verification
- Experience with industry-standard EDA tools such as Cadence, Synopsys, or equivalent.
- Strong understanding of CMOS digital design and semiconductor fundamentals.
- Good scripting/programming skills in Tcl, Python, Perl, or Shell.
- Strong analytical and problem-solving skills.
Preferred Qualifications
- Experience working on advanced process nodes and high-performance SoCs.
- Experience with block-level and/or full-chip physical design.
- Experience with multi-voltage/multi-clock designs.
- Knowledge of UPF/low-power design methodologies.
- Experience with IR/EM analysis and signal integrity.
- Experience with physical design automation and flow development.
- Exposure to SerDes, PCIe, CXL, Ethernet, memory interfaces, or other high-speed connectivity technologies would be an advantage.
- Experience taking designs through full physical signoff and tapeout.
What You’ll Get to Work On
At Astera Labs, you will have the opportunity to work on cutting-edge connectivity solutions for AI and cloud infrastructure, collaborating with experienced semiconductor engineers across architecture, RTL, verification, DFT, and physical design.
You will be part of a highly collaborative engineering environment where your work directly contributes to delivering high-performance, high-bandwidth semiconductor products.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Company
Company facts come from this company's own listings. We only show what the postings themselves carry.