AIML enhanced Design/Verification Methodology Engineer

We are seeking a Design/Verification Engineer to develop and execute verification strategies for complex digital designs using AIML enhanced methodologies. You will architect and maintain UVM-based testbench environments and collaborate with design teams. Ideal candidates have hands-on experience in ASIC or SoC design and strong AIML expertise.

Skills

• systemverilog
• uvm-based testbench development
• aiml methodologies
• verification plan development
• root cause analysis
• synopsys vcs
• cadence xcelium
• mentor questa
• rtl automation
• digital design fundamentals
• chip design
• soc design
• simulation tools
• functional coverage assertions
• systemverilog constraints
• systemverilog assertions/sva
• coverage-driven verification closure
• cross-functional collaboration
• effective communication
• jaspergold
• vc formal
• palladium
• protium
• veloce
• python
• perl
• tcl
• networking
• ethernet
• pcie