Senior ASIC Verification Engineer

Become part of our team as a Senior ASIC Verification Engineer, leading block-level and subsystem verification for advanced networking chips. Drive test planning and coverage closure, and collaborate with cross-functional teams. Ideal for experienced professionals with deep expertise in ASIC/SoC verification and strong knowledge of UVM and SystemVerilog.

Skills

• random testing
• scheduling pipelines
• packet processing
• mentor questa
• coverage analysis
• networking asics
• post-silicon bring-up
• soc debugging
• waveform debugging
• uvm methodology
• test plan development
• cadence xcelium
• asic verification
• system integration
• systemverilog
• synopsys vcs
• coverage analytics
• forwarding engines
• low-power verification
• hardware acceleration